Static random access memory (SRAM), as one of memory devices, has advantages including high speed, low power consumption, and compatibility with industry standard technologies. SRAM is widely used in areas such as personal computers (PC), personal communications, and consumer electronic products (e.g., smart cards, digital cameras, and multimedia players).
FIG. 1 is a schematic illustrating a circuit of a memory cell of a conventional six-transistor (6T) SRAM memory. The memory cell includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4.
The first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 form a bistable circuit. The bistable circuit forms a latch for latching data information. The first PMOS transistor P1 and the second PMOS transistor P2 are pull-up transistors. The first NMOS transistor N1 and the second NMOS transistor N2 are pull-down transistors. The third NMOS transistor N3 and the fourth NMOS transistor N4 are transfer transistors.
A gate of the first PMOS transistor P1, a gate of the first NMOS transistor N1, a drain of the second PMOS transistor P2, a drain of the second NMOS transistor N2, and a source of the fourth NMOS transistor N4 are electrically connected forming a first storage node 11. A gate of the second PMOS transistor P2, a gate of the second NMOS transistor N2, a drain of the first PMOS transistor P1, a drain of the first NMOS transistor N1, and a source of the third NMOS transistor N3 are electrically connected forming a second storage node 12.
Gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are electrically connected to a word line WL. A drain of the third NMOS transistor N3 is electrically connected to a first bit line BL. A drain of the fourth NMOS transistor N4 is electrically connected to a second bit line (complementary bit line) BLB. A source of the first PMOS transistor P1 and a source of the second PMOS transistor P2 are electrically connected to a power supply line Vdd. A source of the first NMOS transistor N1 and a source of the second NMOS transistor N2 are electrically connected to a ground line Vss.
In a read operation of the SRAM memory, current may flow from the first bit line BL and the second bit line BLB that are set at a high level to the first storage node 11 or the second storage node 12 that is set at a low level. In a write operation of the SRAM memory, current may flow from the first storage node 11 or the second storage node 12 that is set at a high level to the first bit line BL or the second bit line BLB that is set at a low level.
However, SRAM memories face challenges in reading/writing stability, as process node shrinks in complementary metal-oxide-semiconductor (CMOS) manufacturing processes with reduced operating voltages and increased variations of threshold voltages due to random doping. To allow an SRAM memory to be stably operated, it is necessary to increase read and write margins of the SRAM memory.
Therefore, there is a need to provide MOS transistors, SRAM memory cell circuits, and fabrication methods to increase read and write margins of an SRAM memory.